A scheduler in a packet switch typically selects packets in a clock cycle of a clock signal in the packet switch. In turn, a switch fabric in the packet switch routes the selected packets through the switch fabric in this next clock cycle of the clock signal. In this way, the scheduler selects the packets in a scheduling cycle and the switch fabric routes the packets in a corresponding routing cycle.
In one type of packet switch, the scheduler schedules packets in a scheduling cycle based on a credit-based flow control protocol and according to ordering rules. Moreover, the scheduler performs scheduling functions in a single clock cycle of a clock signal in the packet switch. In this type of packet switch, the scheduler identifies packets stored in ingress ports of the packet switch for routing to egress ports of the packet switch based on credits advertised by the egress ports. The scheduler then selects at least some of the identified packets stored in the ingress ports that may be simultaneously routed from the ingress ports to egress ports of the packet switch through the switch fabric. Additionally, the scheduler updates the credits advertised by the egress ports based on credits consumed for routing the selected packets. Further, the scheduler updates the credits advertised by the egress ports based on credits released when packets are output from the egress ports. Because the scheduler performs all of these scheduling functions in a single clock cycle of the clock signal, a maximum frequency of the clock signal is often constrained by propagation delays in logic circuitry of the scheduler for performing the scheduling functions, which in turn constrains maximum packet throughput of the packet switch.
Furthermore, the packet switch determines an order for routing packets from an ingress port of the packet switch to egress ports of the packet switch based on the ordering rules. The ordering rules indicate when a packet in a sequence of packets received at an ingress port of the packet switch is allowed or required to be routed ahead of a previous packet in the sequence when the previous packet is blocked in the packet switch. Because the packet switch routes packets from the ingress port to the egress ports based on the ordering rules, logic circuitry of the scheduler for performing the scheduling functions is more complex than other packet switches that do not implement the ordering rules. As a result, propagation delays in the logic circuitry of the scheduler for performing the scheduling functions are increased as compared to these other packet switches that do not implement the ordering rules.